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RISC-V
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The RISC-V ISA is provided under open source licenses that do not require fees to use.
More information about RISC-V can be found at:
https://riscv.org/
Quick guides
Sipeed Longan GD32VF103CBT6 MCU Nano RISC-V Development Board
Programming the Sipeed Longan Nano using Visual Code and PlatformIO and upload to development board
Sipeed RV Debugger Plus
Using Sipeed RV Debugger Plus to upload firmware and to debug code
How to display the Bad Apple video and Sipeed logo on the Sipeed Longan Nano TFT display
How to create bmp.bin and logo.bin files to be displayed on the Sipeed Logan Nano TFT display
How to build the Nuclei RISC-V GNU Compiler Toolchain (riscv-gnu-toolchain) on macOS
How to build Spike emulator and Proxy Kernel (PK) on macOS
How to build RISC-V OpenOCD on macOS
Toolchain riscv-nuclei-elf-gcc (gcc) examples
Create a C library file
Building a program using GD32VF103 Firmware Library and Makefile for GD32VF103 RISC-V microcontroller
RISC-V ASM tutorial
RISC-V ASM tutorial.
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Videos
RISC-V ASM tutorial 1: not available
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