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RISC-V
 
 
RISC-V is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The RISC-V ISA is provided under open source licenses that do not require fees to use.

More information about RISC-V can be found at:
https://riscv.org/


Quick guides







Building a program using the GD32VF103 Firmware Library and Makefile for the GD32VF103 RISC-V microcontroller.



Information
In this tutorial I will be using the following tools:
  • riscv-nuclei-elf-gcc
  • riscv-nuclei-elf-objcopy
  • riscv-nuclei-elf-objdump
  • riscv-nuclei-elf-size
  • Spike emulator
Software prerequisites
How to build the Nuclei RISC-V GNU Compiler Toolchain (riscv-gnu-toolchain) on macOS
How to build Spike emulator and Proxy Kernel (PK) on macOS

Procedure
  • This tutorial is written and tested for the macOS.

  • Goto home directory:
    Type: cd ~

  • Create directory structure:
    Type: mkdir -p gd32v_examples/projects

  • Goto gd32v_examples directory:
    Type: cd gd32v_examples

  • Git clone GD32VF103_Firmware_Library:
    Type: git clone https://github.com/riscv-mcu/GD32VF103_Firmware_Library

  • Git clone platform-gd32v:
    Type: git clone https://github.com/sipeed/platform-gd32v.git

  • Setup a blink demo project:
    Type: cp -Rp platform-gd32v/examples/longan-nano-blink projects
    Type: cp GD32VF103_Firmware_Library/Template/gd32vf103_libopt.h projects/longan-nano-blink/include

  • Download Makefile and place it in directory (without .txt extension):
    ~/gd32v_examples/projects/longan-nano-blink

  • *** Upload firmware and debug with OpenOCD ***

  • Download sipeed-rv-debugger2.cfg and place it in directory (without .txt extension):
    ~/gd32v_examples/GD32VF103_Firmware_Library/Template

    More information about sipeed-rv-debugger2.cfg and OpenOCD:
    Sipeed RV Debugger Plus
    How to build RISC-V OpenOCD on macOS

    Note:
    In the Makefile you will see the following target:

    flash: all
        openocd -f $(TEMPLATE_DIR)/sipeed-rv-debugger2.cfg \
        -c init; halt; \
        -c flash protect 0 0 last off; \
        program firmware.elf verify; \
        mww 0xe004200c 0x4b5a6978; \
        mww 0xe0042008 0x01; \
        resume; exit 0;

    The above mentioned openocd settings were copied from ~/gd32v_examples/platform-gd32v/builder/main.py

  • If needed make changes to the Makefile.
    • DEBUG = 1
      Set debug flag.

    • OPT = -O0
      Set optimization flag.

    • PROJECT = longan-nano-blink
      Set project name.
      Make sure the PROJECT name matches the project directory name.
      ~/gd32v_examples/projects/longan-nano-blink

    • ARCH = -march=rv32imac -mabi=ilp32 -mcmodel=medlow
      Architecture set for Sipeed Longan GD32VF103CBT6 MCU Nano RISC-V Development Board.

  • Connect the Sipeed RV Debugger Plus (on the left) to the Sipeed Longan Nano Development Board (on the right) using 8 female-female jumper wires (12 cm long).
    Connect the USB cable to my macbook.

    More information about:
    Sipeed Longan GD32VF103CBT6 MCU Nano RISC-V Development Board
    Sipeed RV Debugger Plus

    Sipeed RV Debugger Plus and Sipeed Longan Nano 1

    Sipeed RV Debugger Plus and Sipeed Longan Nano 2

    Sipeed RV Debugger Plus and Sipeed Longan Nano 3

    Sipeed RV Debugger Plus and Sipeed Longan Nano 4

    Sipeed RV Debugger Plus and Sipeed Longan Nano 5

    Connections required to upload firmware to the Sipeed Longan Nano Development Board

    Sipeed RV Debugger Plus Sipeed Longan Nano Development Board
    GND GND
    3V3 3V3
    TX RO
    RX TO
    DTR (Not connected) -
    RTS (Not connected) -

    The Sipeed RV Debugger Plus provides 3V3 to the Sipeed Longan Nano Development Board. If the provided 3V3 (by Sipeed RV Debugger Plus) is not sufficient when you connect many other hardware components to the development board, disconnect the 3V3 jumper wire and connect the USB A - USB C cable to the Sipeed Longan Nano Development Board as its power source. Keep the ground jumper wire connected.

    Connections required to debug code

    Sipeed RV Debugger Plus Sipeed Longan Nano Development Board
    GND (Not connected) -
    5V (Not connected) -
    TCK JTCK
    TDI JTDI
    TDO JTDO
    TMS JTMS

  • Check if OpenOCD detects the Sipeed Longan Nano board.

    Type: cd ~
    Type: openocd -f ~/gd32v_examples/GD32VF103_Firmware_Library/Template/sipeed-rv-debugger2.cfg

    Open On-Chip Debugger 0.11.0+dev-02215-gcc0ecfb6d (2022-01-19-15:17)
    Licensed under GNU GPL v2
    For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
    gd32vf103.cpu
    Info : Listening on port 6666 for tcl connections
    Info : Listening on port 4444 for telnet connections
    Info : clock speed 1000 kHz
    Info : JTAG tap: gd32vf103.cpu tap/device found: 0x1000563d
    (mfg: 0x31e (Andes Technology Corporation), part: 0x0005, ver: 0x1)
    Info : JTAG tap: gd32vf103.bs tap/device found: 0x790007a3
    (mfg: 0x3d1 (GigaDevice Semiconductor (Beijing) Inc), part: 0x9000, ver: 0x7)
    Info : [gd32vf103.cpu] datacount=4 progbufsize=2
    Info : Examined RISC-V core; found 1 harts
    Info : hart 0: XLEN=32, misa=0x40901105
    [gd32vf103.cpu] Target successfully examined.
    Info : starting gdb server for gd32vf103.cpu on 3333
    Info : Listening on port 3333 for gdb connections

    Note 1:
    If the Sipeed Longan Nano is not detected:

    • Press BOOT key and keep it pressed.
    • Shortly press and immediately release the RESET button.
    • Then release the BOOT button.

    Note 2:
    If you get the following error:
    Error: couldn't bind tcl to socket on port 6666: Address already in use

    Report a list of all open files and the processes that opened them.
    Type: lsof -i :6666
    Write down the pid_number.
    Type: kill -9 pid_number

  • Clean environment:
    Type: cd ~/gd32v_examples/projects/longan-nano-blink
    Type: make clean

  • Build and upload ~/gd32v_examples/projects/longan-nano-blink/firmware.elf to device:
    Type: make flash

  • Blabla